Phase 3: Caching and Virtual Memory
缓存和虚拟内存
The third phase of Nachos is to investigate the interaction between the TLB, the virtual memory system, and the file system. We don’t provide any new virtual memory code for this assignment. You will continue to use the stub file system. For this phase, you should run gmake and nachos in the proj3 directory.
Nachos的第三个阶段是研究TLB、虚拟内存系统和文件系统之间的交互。我们没有为这个任务提供任何新的虚拟内存代码。您将继续使用存根文件系统。在这个阶段，您应该在proj3目录中运行gmake和nachos。
To help you to organize your code better, we provide you with a new package, nachos. vm, with two new classes, VMKernel and VMProcess. VMKernel extends UserKernel, and VMProcess extends UserProcess. VMKernel and VMProcess are the only classes you should have to modify for this project phase.
为了帮助您更好地组织代码，我们提供了一个新的包nachos。vm，有两个新类:VMKernel和VMProcess。VMKernel扩展了UserKernel，而VMProcess扩展了用户进程。在这个项目阶段，VMKernel和VMProcess是唯一需要修改的类。
This phase and the next phase of the project involve open-ended design problems. We will expect you to come up with a design that would make sense in a real system, and to defend your choices in the design review. For example, you will have some freedom to choose how to do software address translation on TLB misses, how to represent the swap partition, how to implement paging, etc. In each case, we will expect you to come to the design review armed with a defensible justification as to why your choices are reasonable. You should evaluate your design on all the available criteria: speed of handling a TLB miss, space overhead in memory, minimizing the number of page faults, simplicity, etc. There is no single “right” answer.
这个阶段和下一阶段的项目涉及开放式设计问题。我们希望你能设计出一个在真实系统中有意义的设计，并在设计评论中为你的选择辩护。例如,您将有自由选择如何去做软件在TLB地址转换,如何代表交换分区,如何实现分页,等等。在每种情况下,我们将期待你来设计审查手持一个站得住脚的理由为什么你的选择是合理的。你应该根据所有可用的标准来评估你的设计:处理一个TLB失误的速度，内存中的空间开销，最小化页面错误的数量，简单性等等，没有一个“正确”的答案。
The first design aspect to consider is the software-managed translation lookaside buffer (TLB). Page tables were used in phase 2 to simplify memory allocation and to isolate failures from one address space from affecting other programs. For this phase, the processor knows nothing about page tables. Instead, the processor only deals with a software-managed cache of page table entries, called the TLB. Given a memory address (an instruction to fetch, or data to load or store), the processor first looks in the TLB to determine if the mapping of the virtual page to a physical page is already known. If the translation is in the TLB, the processor uses it directly. If the translation is not in the TLB (a “TLB miss”), the processor causes a trap to the OS kernel. Then it is the kernel’s responsibility to load the mapping into the TLB, using page tables, segments, inverted page tables, or whatever other mechanism might be appropriate. In other words, the Nachos MIPS simulator does not have direct access to your page tables; it only knows about the TLB. It is your job to write the code that manages a TLB miss.
首先要考虑的设计方面是软件管理的翻译lookaside buffer(TLB)。第2阶段使用页表来简化内存分配，并从一个地址空间隔离失败，从而影响其他程序。对于这个阶段，处理器对页表一无所知。相反，处理器只处理页面表条目的软件管理缓存，称为TLB。给定一个内存地址(用于获取或数据到加载或存储的指令)，处理器首先在TLB中查找，以确定虚拟页到物理页面的映射是否已经知道。如果翻译在TLB中，处理器直接使用它。如果翻译不是在TLB(一个“TLB miss”)中，处理器会给OS内核造成一个陷阱。然后，内核负责将映射加载到TLB中，使用页表、段、倒页表，或者其他任何可能合适的机制。换句话说，Nachos MIPS模拟器不直接访问您的页表;它只知道TLB。编写管理TLB失误的代码是您的工作。
The second design aspect of this project is paging, which allows physical memory pages to be transferred to and from disk to provide the illusion of an (almost) unlimited physical memory. A TLB miss may require a page to be brought in from disk to satisfy the translation. That is, when a TLB miss fault occurs, the kernel should check its own page table. If the page is not in memory, it should read the page in from disk, set the page table entry to point to the new page, install the page table entry, and resume the execution of the user program. Of course, the kernel must first find space in memory for the incoming page, potentially writing some other page back to disk, if it has been modified.
这个项目的第二个设计方面是分页，它允许将物理内存页面从磁盘传输到磁盘，以提供(几乎)无限物理内存的错觉。一个TLB失误可能需要从磁盘引入一个页面以满足转换。也就是说，当一个TLB错误发生时，内核应该检查它自己的页表。如果页面不在内存中，则应该从磁盘读取页面，设置页面表项以指向新页面，安装页表条目，并恢复用户程序的执行。当然，内核必须首先为传入的页面找到内存空间，如果它被修改的话，可能会将其他页面重新写入磁盘。
Performance of this mechanism depends greatly on the policy used to decide which pages are kept in memory and which are stored on disk. On a page fault, the kernel must decide which page to replace; ideally, it will throw out a page that will not be referenced for a long time, keeping in memory those pages may be referenced soon. Another consideration is that if the replaced page has been modified, the page must first be saved to disk before the needed page can be brought in. (Of course, if the page has not been modified, it is not necessary to write it back to disk.)
这种机制的性能在很大程度上取决于用于决定哪些页面保存在内存中，哪些页面存储在磁盘上。在页面错误上，内核必须决定要替换哪个页面;理想情况下，它会抛出一个长时间不会被引用的页面，记住这些页面可能很快就会被引用。另一个考虑是如果替换的页面已经被修改，那么页面必须先保存到磁盘，然后才可以引入需要的页面。(当然，如果页面没有被修改，就没有必要把它写回磁盘。)
To help you implement virtual memory, each TLB entry contains three status bits: valid, used, and dirty. If the valid bit is set, the virtual page is in memory and the translation can be used directly by the processor. If the valid bit is clear, or if the page translation is not found in the TLB, then the processor traps to the OS to perform the translation. The processor sets the used bit in the TLB entry whenever a page is referenced and sets the the dirty bit whenever the page is modified.
为了帮助您实现虚拟内存，每个TLB条目包含三个状态位:有效、使用和脏。如果设置了有效位，则虚拟页在内存中，而翻译可以直接由处理器使用。如果有效位是清晰的，或者在TLB中没有找到页面转换，那么处理器就会捕捉到操作系统来执行翻译。当页面被引用时，处理器将在TLB条目中使用的位设置为，并在修改页面时设置脏的位。
